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cy29973 3.3 v 125 mhz multi-output zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07291 rev. *f revised march 18, 2014 3.3 v 125 mhz multi-output zero delay buffer features output frequency up to 125 mhz 12 clock outputs: frequency configurable 350 ps max. output to output skew configurable output disable two reference clock inputs for dynamic toggling oscillator or pecl reference input spread spectrum compatible glitch-free output clocks transitioning 3.3 v power supply pin compatible with mpc973 industrial temperature range: ?40 c to +85 c 52-pin tqfp package frequency table [1] vc0_sel fb_sel2 fb_sel1 fb_sel0 f vc0 00008x 000112x 001016x 001120x 010016x 010124x 011032x 011140x 10004x 10016x 10108x 101110x 11008x 110112x 111016x 111120x note 1. x = reference input frequency, 200 mhz < f vco < 480 mhz.
cy29973 document number: 38-07291 rev. *f page 2 of 15 logic block diagram ref_sel 0 1 0 1 phase detector vco lpf sync frz d q qa0 sync frz d q sync frz d q sync frz d q sync frz d q sync frz d q 0 1 /2 power-on reset output disable circuitry data generator /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 /4, /6, /8, /10 sync pulse pecl_clk pecl_clk# tclk0 tclk1 tclk_sel fb_in fb_sel2 mr#/oe sela(0,1) 2 selb(0,1) 2 selc(0,1) 2 fb_sel(0,1) 2 sclk sdata inv_clk qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 fb_out sync 12 vco_sel pll_en
cy29973 document number: 38-07291 rev. *f page 3 of 15 contents pinouts .............................................................................. 4 pin definitions [2] .............................................................. 5 description ........................................................................ 6 zero delay buffer .............................................................. 6 glitch-free output frequency transitions .................... 6 sync output ..................................................................... 7 power management .......................................................... 8 absolute maximum conditions ....................................... 9 dc electrical specifications ............................................ 9 ac electrical specifications .......................................... 10 ordering information ...................................................... 11 ordering code definitions ......................................... 11 package drawing and dimensions ............................... 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history page ................................................. 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc? solutions ...................................................... 15 cypress developer community ................................. 15 technical support ................. .................................... 15
cy29973 document number: 38-07291 rev. *f page 4 of 15 pinouts vss mr#/oe sclk sdata fb_sel2 pll_en ref_sel tclk_sel tclk0 tclk1 pecl_clk pecl_clk# vdd fb_sel1 sync vss qc0 vddc qc1 selc0 selc1 qc2 vddc qc3 vss inv_clk selb1 selb0 sela1 sela0 qa3 vddc qa2 vss qa1 vddc qa0 vss vco_sel vss qb0 vddc qb1 vss qb2 vddc qb3 fb_in vss fb_out vddc fb_sel0 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 cy29973
cy29973 document number: 38-07291 rev. *f page 5 of 15 pin definitions [2] pin name pwr i/o type description 11 pecl_clk i pu pecl clock input. 12 pecl_clk# i pd pecl clock input. 9 tclk0 i pu external reference or test clock input. 10 tclk1 i pu external reference or test clock input. 44, 46, 48, 50 qa(3:0) vddc o clock outputs. see divider table on page 6 for frequency selections. 32, 34, 36, 38 qb(3:0) vddc o clock outputs. see divider table on page 6 for frequency selections. 16, 18, 21, 23 qc(3:0) vddc o clock outputs. see divider table on page 6 for frequency selections. 29 fb_out vddc o feedback clock output. connect to fb_in for normal operation. the divider ratio for this output is set by fb_sel(0:2). see frequency table [1] on page 1 . a bypass delay capacitor at this output control input reference or output banks phase relationships. 25 sync vddc o synchronous pulse output. this ou tput is used for system synchronization. the rising edge of the output pulse is in sync with both the rising edges of qa (0:3) and qc(0:3) output clocks regardl ess of the divider ratios selected. 42, 43 sela(1,0) i pu frequency select inputs. these inputs select the divider ratio at qa(0:3) outputs. see divider table on page 6 . 40, 41 selb(1,0) i pu frequency select inputs. these inputs select the divider ratio at qb(0:3) outputs. see divider table on page 6 . 19, 20 selc(1,0) i pu frequency select inputs. these inputs select the divider ratio at qc(0:3) outputs. see divider table on page 6 . 5, 26, 27 fb_sel(2:0) i pu feedback select inputs. these inputs select the divide ratio at fb_out output. see frequency table [1] on page 1 . 52 vco_sel i pu vco divider select input. when se t low, the vco output is divided by 2. when set high, the divider is bypassed. see frequency table [1] on page 1 . 31 fb_in i pu feedback clock input. connect to fb_out for accessing the pll. 6 pll_en i pu pll enable input. when asserted high, pll is enabled. when low, pll is bypassed. 7 ref_sel i pu reference select input. when high, the pecl inputs are selected. when low, tclk[0:1] are selected. 8 tclk_sel i pu tclk select input. when low, tclk0 is selected. when high tclk1 is selected. 2 mr#/oe i pu master reset or output enable inpu t. when asserted low, resets all of the internal flip-flops and also disables all of the outputs. when pulled high, releases the internal flip-flops from reset and enables all of the outputs. 14 inv_clk i pu inverted clock input. when set high, qc(2,3) outputs are inverted. when set low, the inverter is bypassed. 3 sclk i pu serial clock input. clocks data at sdata into the internal register. 4 sdata i pu serial data input. input data is clocked to the internal register to enable or disable individual outputs. this prov ides flexibility in power management. 17, 22, 28, 33,37, 45, 49 vddc 3.3v power supply for output clock buffers. 13 vdd 3.3v supply for pll. 1, 15, 24, 30, 35, 39, 47, 51 vss common ground. note 2. a bypass capacitor (0.1 ? f) must be placed as close as possible to each positive power (<0.2?). if these bypass capacitors are not close to the pins the ir high frequency filtering characteristics is cancelled by the lead inductance of the traces.
cy29973 document number: 38-07291 rev. *f page 6 of 15 description the cy29973 has an integrated pll that provides low-skew and low-jitter clock outputs for hi gh-performance microprocessors. three independent banks of four outputs and an independent pll feedback output, fb_out, provide exceptional flexibility for possible output configurations. the pll is ensured stable operation given that the vco is configured to run between 200 mhz to 480 mhz. this allows a wide range of output frequencies up to125 mhz. the phase detector compares the input reference clock to the external feedback input. for normal operation, the external feedback input, fb_in, is conne cted to the feedback output, fb_out. the internal vco is r unning at multiples of the input reference clock set by fb_sel(0:2) and vco_sel select inputs, refer to frequency table [1] on page 1 . the vco frequency is then divided down to provide t he required output frequencies. these dividers are set by sela(0,1), selb(0,1), selc(0,1) select inputs, see divider table . for situations were the vco needs to run at relatively lo w frequencies and hence might not be stable, assert vco_sel low to divide the vco frequency by 2. this maintains the desired output relationships, but provides an enhanced pll lock range. the cy29973 is also capable of pr oviding inverted output clocks. when inv_clk is asserted high, qc2 and qc3 output clocks are inverted. these clocks could be used as feedback outputs to the cy29973 or a second pll dev ice to generate early or late clocks for a specific design. this inversion does not affect the output to output skew. zero delay buffer when used as a zero delay buffer the cy29973 is likely to be in a nested clock tree application. for these applications the cy29973 offers a low voltage pecl clock input as a pll reference. this allows the user to use lvpecl as the primary clock distribution device to take advantage of its far superior skew performance. the cy29973 then can lock onto the lvpecl reference and translate with near zero delay to low skew outputs. by using one of the outputs as a feedback to the pll the propagation delay through the device is eliminated. the pll works to align the output edge wit h the input reference edge thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. because th e static phase offset is a function of the reference clo ck the tpd of the cy29973 is a function of the configuration used. glitch-free output fr equency transitions customarily when output buffers have their internal counters changed ?on the fly? their output clock periods will: 1. contain short or ?runt? clo ck periods. these are clock cycles in which the cycle(s) are shorte r in period than either the old or new frequency that is being transitioned to. 2. contain stretched clock periods. these are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. this device specifically includes logic to guarantee that runt and stretched clock pulses do not occu r if the device logic levels of any or all of the following pins changed ?on the fly? while it is operating: sela, selb , selc, and vco_sel. divider table vco_sel sela1 sela0 qa selb1 selb0 qb selc1 selc0 qc 0 0 0 vco/8 0 0 vco/8 0 0 vco/4 0 0 1vco/120 1vco/120 1 vco/8 0 1 0vco/161 0vco/161 0vco/12 0 1 1vco/241 1vco/201 1vco/16 1 0 0 vco/4 0 0 vco/4 0 0 vco/2 1 0 1 vco/6 0 1 vco/6 0 1 vco/4 1 1 0 vco/8 1 0 vco/8 1 0 vco/6 1 1 1vco/121 1vco/101 1 vco/8
cy29973 document number: 38-07291 rev. *f page 7 of 15 sync output in situations were output frequency relationships are not integer multiples of each other the sy nc output provides a signal for system synchronization. the cy29973 monitors the relationship between the qa and the qc output clocks. it provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the qa and qc outputs. the duration and the placemen t of the pulse depend on the higher of the qa and qc output frequen cies. the following timing diagram illustrates various waveforms for the sync output. note that the sync output is defined for all possible combinations of the qa and qc outputs even though under some relationships the lower frequency clo ck could be used as a synchronizing signal. figure 1. sync output for different input and out ratio sync qc qa sync qc qa sync qa qc sync qc qa sync qa qc sync qc qa sync qc qa vco 1:1 mode 2:1 mode 3:1 mode 3:2 mode 4:1 mode 4:3 mode 6:1 mode
cy29973 document number: 38-07291 rev. *f page 8 of 15 power management the individual output enable or freeze control of the cy29973 allows the user to implement unique power management schemes into the design. the outputs are stopped in the logic ?0? state when t he freeze control bits are activated. the serial input registe r contains one programmable freeze enable bit for 12 of the 14 output cloc ks. the qc0 and fb_out outputs can not be frozen with the serial port, this avoids any potential lock up situation must an error occur in the loading of the serial data. an output is frozen wh en a logic ?0? is programmed and enabled when a logic ?1? is written. t he enabling and freezing of individual outputs is done in such a ma nner as to eliminate the possibi lity of partial ?runt? clocks. the serial input register is programmed through the sdata input by writing a logic ?0? start bit followed by 12 nrz freeze enab le bits. the period of each sdata bit equals the period of the free runn ing sclk signal. the sdata is sampled on the rising edge of sclk . figure 2. control bit map d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d0-d3 are the control bits for qa0-qa3, respectively d4-d7 are the control bits for qb0-qb3, respectively d8-d10 are the control bits for qc1-qc3, respectively d11 is the control bit for sync start bit
cy29973 document number: 38-07291 rev. *f page 9 of 15 absolute maximum conditions exceeding maximum ratings [3] may shorten the useful life of the device. user guidelines are not tested. maximum input voltage relative to v ss : ........... v ss ? 0.3 v maximum input voltage relative to v dd : ........... v dd + 0.3 v storage temperature: ... ............ ............... ?65 ? c to +150 ? c operating temperature: ............................. ?40 ? c to +85 ? c maximum esd protection .............................................. 2 kv maximum power supply: .............................................. 5.5 v maximum input current: ????????????????????????????????????????????????? 20 ma this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions must be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out must be constrained to the range: v ss < (v in or v out ) < v dd unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc electrical specifications v dd = 2.9 v to 3.6 v, v ddc = 3.3 v 10%, t a = ?40 ? c to +85 ? c parameter description conditions min typ max unit v il input low voltage v ss ?0.8 v v ih input high voltage 2.0 ? v dd v v pp peak-to-peak input voltage pecl_clk 300 ? 1000 mv v cmr common mode range pecl_clk [4] v dd ? 2.0 ? v dd ? 0.6 v i il input low current [5] ? ? ?120 ? a i ih input high current [5] ??120 ? a v ol output low voltage [6] i ol = 20 ma ? ? 0.5 v v oh output high voltage [6] i oh = ?20 ma 2.4 ? ? v i ddq quiescent supply current ?1015ma i dda pll supply current v dd only ? 15 20 ma i dd dynamic supply current qa and qb at 60 mhz, qc at 120 mhz, cl=30 pf ?225? ma qa and qb at 25 mhz, qc at 50 mhz, cl=30 pf ?125? c in input pin capacitance ? 4 ? pf z out output impedance 15 18 22 ? notes 3. multiple supplies: the voltage on any input or io pin cannot exceed the power pin during power up. power supply sequencing is not required. 4. the v cmr is the difference from the most positive side of the different ial input signal. normal operation is obtained when the ?high? i nput is within the v cmr range and the input lies within the v pp specification. 5. inputs have pull up/pull down resistors that effect input current. 6. driving series or parallel terminated 50 ? (or 50 ? to v dd /2) transmission lines.
cy29973 document number: 38-07291 rev. *f page 10 of 15 ac electrical specifications v dd = 2.9 v to 3.6 v, v ddc = 3.3 v 10%, t a = ?40 ? c to +85 ? c [7] parameter description conditions min typ. max unit tr/tf tclk input rise or fall ? 3.0 ns fref reference input frequency note 8 ? note 8 mhz frefdc reference input duty cycle 25 ? 75 % fvco pll vco lock range 200 ? 480 mhz tlock maximum pll lock time ? ? 10 ms tr/tf output clocks rise or fall time [9] 0.8 v to 2.0 v 0.15 ? 1.2 ns fout maximum output frequency q ( ? 2) ? ? 125 mhz q ( ? 4) ? ? 120 q ( ? 6) ? ? 80 q ( ? 8) ? ? 60 foutdc output duty cycle [9] tcycle/2 ? 750 ? tcycle/2 + 750 ps tpzl, tpzh output enable time [9] (all outputs) 2?10ns tplz, tphz output disable time [9] (all outputs) 2?8ns tccj cycle to cycle jitter [9] (peak to peak) ?100?ps tskew any output to any output skew [9, 10] ?250350ps propagation delay [10, 11] pecl_clk ?225 ?25 175 ps tpd tclk0 qfb =(38) ?70 130 330 tclk1 ?130 70 270 notes 7. parameters are guaranteed by design and charac terization. not 100% tested in production. 8. maximum and minimum input referenc e is limited by vc0 lock range. 9. outputs loaded with 30pf each. 10. 50 ? transmission line terminated into vdd/2. 11. tpd is specified for a 50mhz input reference. tpd does not include jitter.
cy29973 document number: 38-07291 rev. *f page 11 of 15 ordering code definitions ordering information part number package type production flow pb-free CY29973AXI 52-pin tqfp industrial, ?40 c to +85 c CY29973AXIt 52-pin tqfp ? tape and reel industrial, ?40 c to +85 c t = tape and reel temperature range: x = c or i c = commercial; i = industrial pb-free package type: a = 52-pin tqfp base device part number company id: cy = cypress cy 29973 a x t x
cy29973 document number: 38-07291 rev. *f page 12 of 15 package drawing and dimensions figure 3. 52-pin tqfp (10 10 1.0 mm) package outline, 51-85158 51-85158 *c
cy29973 document number: 38-07291 rev. *f page 13 of 15 acronyms document conventions units of measure acronym description i/o input/output lvpecl low voltage positive/pseudo emitter coupled logic pecl positive/pseudo emitter coupled logic pll phase locked loop tqfp thin quad flat pack vco voltage-controlled oscillator symbol unit of measure c degree celsius hz hertz khz kilohertz kv kilovolt mhz megahertz a microampere f microfarad ma milliampere ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad ps picosecond vvolt wwatt
cy29973 document number: 38-07291 rev. *f page 14 of 15 document history page document title: cy29973, 3.3 v 125 mhz multi-output zero delay buffer document number: 38-07291 rev. ecn orig. of change submission date description of change ** 111102 brk 02/07/02 new data sheet *a 122883 rbi 12/22/02 added power up requirements to maximum ratings *b 200081 rgl 01/22/04 added z out specifications in the dc electrical specs changed the package drawing and dimension to cy standard *c 2562606 aesa 09/09/08 updated template. added note ?not recommended for new designs.? added part number CY29973AXI and CY29973AXIt in ordering information table. *d 2904743 cxq 04/05/2010 removed inactive part numbers cy29973ai and cy29973ait. updated package diagram. *e 3163592 cxq 02/05/2011 added ordering code definitions under ordering information . added acronyms and units of measure . updated in new template. *f 4312848 cinm 03/18/2014 updated package drawing and dimensions : spec 51-85158 ? changed revision from *a to *c. updated in new template. completing sunset review.
document number: 38-07291 rev. *f revised march 18, 2014 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy29973 ? cypress semiconductor corporation, 2002-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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